LPM_FIFO+ problem

Hi Kaz,

The write clock is a 4MHz clock, created from a master 32MHz clock. The wrreq pulse is timed to be wide enough to accept one 4MHz clock edge. The rdreq is asynchronous in that no fixed clock will give me a guaranteed clock edge during the time that rdreq is high, so I have taken the rdreq signal, delayed it by 60nS and used it as the rdclk to clock the data through the fifo. The wrreq and rdreq signals are only about 120nS wide. The design works just fine, apart from the first time the fifo is read after a reset. I have to read out two null value words before the valid data apears at the output. Once those two null words have been flushed out of the fifo, the design is absolutely solid without loss of data for hours with millions of read/writes. This anomaly is experienced in both fifos that use the same basic idea.