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Honored Contributor
Honored ContributorLPM_Counter odd behavior
Hi guys, I'm fairly new to using Quartus (and FPGAs in general), and so I thought I would check out some of the LPM megafunctions. This was my schematic for a simple counter (using LPM_Counter): ...
Altera_ForumHonored Contributor
Honored ContributorYou get first answers when reading the synthesis report throughly. It will be reporting about registers having no defined POR state. Rather than ignoring this message, you should apply a reset signal in your simulation.
The problem is the usage of both asynchronous set and reset for several register bits, which should be avoided if ever possible. It's emulated by latch and XOR construct. Besides reduced timing performance, undefined POR state is a result of this construct. P.S.: The said Quartus warning is --- Quote Start --- Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state. Warning (13310): Register xxxx is converted into an equivalent circuit using register yyyy and latch zzzz --- Quote End ---
