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Altera_Forum's avatar
Altera_Forum
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13 years ago

LPM_Counter odd behavior

Hi guys, I'm fairly new to using Quartus (and FPGAs in general), and so I thought I would check out some of the LPM megafunctions. This was my schematic for a simple counter (using LPM_Counter):

https://www.alteraforum.com/forum/attachment.php?attachmentid=6924

When I performed a timing simulation of this circuit, I get this:

https://www.alteraforum.com/forum/attachment.php?attachmentid=6926

My questions are:

(1) What's with the unknown values? Why do q[5], q[4], and q[1] have values of undefined (X) (0000110010 seems to be 50, my LPM_AVALUE)?

(2) What should I do to actually make this counter work from the get-go? (Apparently, manually setting the rst line to high once will make the counter work, but how can I make the counter reset automatically?)

I'm using Quartus II v9.0, working with the Cyclone II EP2C20F484C7.

I appreciate any help I can get. Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You get first answers when reading the synthesis report throughly. It will be reporting about registers having no defined POR state. Rather than ignoring this message, you should apply a reset signal in your simulation.

    The problem is the usage of both asynchronous set and reset for several register bits, which should be avoided if ever possible. It's emulated by latch and XOR construct. Besides reduced timing performance, undefined POR state is a result of this construct.

    P.S.: The said Quartus warning is

    --- Quote Start ---

    Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

    Warning (13310): Register xxxx is converted into an equivalent circuit using register yyyy and latch zzzz

    --- Quote End ---