Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

LPDDR2 Interfacing to CycloneV

Hi,

In general, from Board design perspective,

What is the process (with quartus SW) for planing LPDDR2 interface on CycloneV?

For example how to determine which BANK/IO to use

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I strongly recommend you put a simple FPGA design together (it need only be simple), instantiating the LPDDR interface, run it through Quartus and let Quartus choose a pinout.

    Decide if you can work with that. If so, great. If not constrain it to use your preferred bank(s) and run that through Quartus again.

    Remember, you will always be able to shuffle DQ pins within a byte lane.

    Cheers,

    Alex