Low Voltage Cyclone III Configuration

From the Stratix II GX pin connection guidelines:

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These pins are internally connected through a 5-kΩ resistor to GND. Do

not leave these pins floating. When these pins are unused, connect them

to GND. Depending on the configuration scheme used, these pins should

be tied directly to VCCPD or GND. Refer to the Configuring Stratix II and

Stratix II GX Devices chapter in volume 1 of the Configuration

Handbook. If only JTAG configuration is used, connect these pins to

ground.

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And from the Stratix II GX User's Guide:

The configuration scheme is selected by driving the Stratix II or

Stratix II GX device MSEL pins either high or low as shown in Table 13–1.

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The MSEL pins are powered by the VCCIO power supply of the bank they

reside in. The MSEL[3..0] pins have 9-kΩ internal pull-down resistors

that are always active. During power-on reset (POR) and during

reconfiguration, the MSEL pins have to be at LVTTL VIL and VIH levels to

be considered a logic low and logic high.

1 To avoid any problems with detecting an incorrect configuration

scheme, hard-wire the MSEL[] pins to VCCPD and GND, without

any pull-up or pull-down resistors. Do not drive the MSEL[]

pins by a microprocessor or another device.

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However, I did disregard this council somewhat as I wired them too a DIP switch that when closed pulled them directly to 3.3V and when open pulled them through 10K resistors to ground.

Jake