Low Pass IIR filter using cyclone II FPGA

Greetings Koce, I don't know how far you got with this so some of this may be known to you: To implement the filter on a FPGA using DSP builder, you need a series of delay lines which represent the (n-1), (n-2), etc, taps. Signed integer constants, one for every co-efficient (You could also use signed fractional constants to approximate a floating point number). Then using a multiplier block for every coefficient, you then multiply the coefficient with the corresponding delay tap. Then add the result all up using a parallel adder. Of course there are DSP builder blocks that have multiple delay taps and combinations of adders and multipliers. There is also a trick to reducing the amount of resources used if you have a symmetrical filter, and that is to add the outputs of the delay lines that feed the same value coefficient before they are multiplied with it, then you need less multipliers and less inputs on your parallel adder. If you need more clarification please send me an email on [email protected]