Loss of FPGA configuration

> Did you try to stop the affected system parts, including the PLL with an asynchronous reset?

I replaced the clock gating by the reset (global_reset_n of DDR2 IP) as you indicated. On the board I'm currently working on, the error does not show up anymore. I even may gate the clock subsequently to the reset without any harm.

However: I still observe significant power supply dip on VCCL(1.1V) and VCCPD (2.5V) when activating the reset (without clock gating), and I assume the POR did just not trigger (but may do so on another device...). Maybe I have some illegal bank voltage combination (did check that, but found no offending conditions so far)?

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This is how my topology looks like (EP3SL50780):

P28, CLK1p, Bank 1C, 3.3V : 50 MHz clock input to general PLL

AH15, CLK5n, Bank 3C, 1.8V : Direct feed (here was the gate) from P28

A14, CLK13n, Bank 7C, 1.8V : Direct feed (here was the gate) from P28

Memory interface AB:

AG15, CLK5p, Bank 3C, 1.8V : 50 MHz DDR PLL clock input (fed from AH15)

Memory interface uses banks: 3A, 3C, 4A

Memory interface CD:

B14, CLK13p, Bank 7C, 1.8V : 50 MHz DDR PLL clock input (fed from A14)

Memory interface uses banks: 7A, 7C, 8A

PLL outputs of both memory interface are merged as indicated by AN462, most of the design is clocked with the merged phy_clk (200 MHz, fanout 17679). This is the clock I intend to stop for sleep mode.

My general power supply concept looks like this:

1V1_VCCL : All 24 VCLL

1V1_VCC : All 8 VCC

1V1_VCCD1 : VCCD_PLL_B1

1V1_VCCD2 : VCCD_PLL_L2

1V1_VCCD3 : VCCD_PLL_R2

1V1_VCCD4 : VCCD_PLL_T1

1V8 . VCCIO1A/2A/3A/3C/4A/4C/5A/6A/7A/7C/8A/

2V5 : VCC_CLKIN3C/4C/7C/8C

VCCBAT

VCCPD1A/2A/3A/3C/4A/4C/5A/5C/6A/6C/7A/7C/8A

VCCIO5C/6C

2V5_VCCPT : All 8 VCCPT

2V5_A : VCCA_PLL_B1/L2/R2/T1

3V3 : All 2 VCCPGM

VCCPD1C/2C/8C

VCCIO8C