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Honored Contributor
Honored ContributorLoss of FPGA configuration
To minimize power consumption, I have the Oscillator input of the main part of my Stratix III design gated (glitchfree keeping low, if gated). Connected to this clock (50 MHz) are two synchron...
Altera_ForumHonored Contributor
Honored ContributorThanks for sharing your thoughts. Out of these, I've got some further questions:
- In my setup, the CONFIGn is stable, therefor, I assume that POR is triggered. Which of the supply voltages that are monitored by POR would you expect to dipp assumed the PLL is "running wild"? - Are there other indicators to make out whether the PLL is the "bad" guy (I can not see the PLL output clock going mad)? - I use two synchronized DDR2 I/F with internal PLL, therefor, access to the PLL (to directly gate ate the clock output drivers) seems not trivial for me. Until now, I wasn't able to have external DDR2 PLL synchronized. Therefor, I intend to reduce the clock to a very low one instead of completely switching it off. May this be viable?
