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Altera_Forum's avatar
Altera_Forum
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16 years ago

lookup table help..

hi there,

i'm new in fpga design and i need someone to teach me how to make lookup table for save the data and call to lcd display.

So if anyone has any suggestions or can offer any help I'd be very grateful. Thank you very much.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    thanks for the info.i have done reading some of the book and i still didn't know how to make it.i found that some coding are similar to c language and i don't know if it suitable for quatus software.i hope that somebody can help me.

    tq.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    amilcar is right. You have to understand the basic concepts of programmable logic hardware description languages to to start with your application problem.

    Your problem description is rather vague. I don't e.g. see, how a lookup table is related to "saving the data". Saving which to data to what? "Call to lcd display" - Which kind of lcd display, which representation of data?

    In my opinion, programmable logic is not the first choice for sending data to a display, although it's possible of course. Altera development kit examples are mostly using a software processor (Nios II) to perform similar tasks. Lookup tables are easily achieved by a FPGA internal ROM.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Actually,i want to design a memory that can save name,address,etc. and display it to lcd display.example,if i want to show someone name,i just type their name on keypad and it will show on lcd display.i dont know how to design it in easier way.i thought that i can use lookup table to design it.

    any suggestions or help I'd be very grateful.

    tq
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    That is a hard to solve problem for a beginer. You should start with simpler problems, follow some of the many many tutorials on the net, choose one language, SystemVerilog or VHDL. Do not use Verilog it sucks, but SystemVerilog is OK.