Forum Discussion
Altera_Forum
Honored Contributor
11 years agoAs I said, i'm mor into VHDL than Verilog.
Please use CODE-Tags if you want to write Code in your Post. It makes debugging easier. What is your Error-Message? I think you have forgotten to close some of your if statements. This is how I read your code:localparam State1 = 0;
localparam State2 = 1;
reg rCntr;
reg rTmCntr1, rTmCntr2;
reg wPwm, StateSignal, SwitchSignal;
initial begin
rTmCntr1 = 0;
rTmCntr2 = 0;
rCntr = 2000000;
wPwm = 0;
StateSignal = State1;
SwitchSignal = 0;
end
always @(posedge c0) begin
if (SwitchSignal == 1)
StateSignal = State2;
end
always @(posedge c0) begin
if (StateSignal == State1) begin
// code for State1
if (Enable == 1'b1) begin
rTmCntr1 <= rTmCntr1 + 1'b1;
if (rTmCntr1 < 2500)
wPwm <= 1;
else if (rTmCntr1 > 2500)
wPwm <= 0;
if (rTmCntr1 == 5000)
rTmCntr1 <= 1'b0;
end
if (rCntr > 0)
rCntr <= rCntr - 1'b1;
else if (rCntr == 10)
SwitchSignal = 1;
end
else begin
// code for State2
if (Enable == 1'b1) begin
rTmCntr2 <= rTmCntr2 + 1'b1;
if (rTmCntr2 < 1250)
wPwm <= 1;
else if (rTmCntr2 > 5000)
wPwm <= 0;
if (rTmCntr2 == 5000)
rTmCntr2 <= 1'b0;
end
end
end And this is how I think it should work (better): localparam State1 = 0;
localparam State2 = 1;
reg rCntr;
reg rTmCntr1, rTmCntr2;
reg wPwm, StateSignal, SwitchSignal;
initial begin
rTmCntr1 = 0;
rTmCntr2 = 0;
rCntr = 2000000;
wPwm = 0;
StateSignal = State1;
SwitchSignal = 0;
end
always @(posedge c0) begin
if (SwitchSignal == 1)
StateSignal = State2;
end
always @(posedge c0) begin
if (StateSignal == State1) begin
// code for State1
if (Enable == 1'b1) begin
rTmCntr1 <= rTmCntr1 + 1'b1;
if (rTmCntr1 < 2500)
wPwm <= 1;
else if (rTmCntr1 > 2500)
wPwm <= 0;
if (rTmCntr1 == 5000)
rTmCntr1 <= 1'b0;
end
if (rCntr > 0)
rCntr <= rCntr - 1'b1;
else if (rCntr == 10)
SwitchSignal = 1;
end
end
end
else begin
// code for State2
if (Enable == 1'b1) begin
rTmCntr2 <= rTmCntr2 + 1'b1;
if (rTmCntr2 < 1250)
wPwm <= 1;
else if (rTmCntr2 > 5000)
wPwm <= 0;
if (rTmCntr2 == 5000)
rTmCntr2 <= 1'b0;
end
end
end