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Altera_Forum
Honored Contributor
Honored ContributorLooking for state machine in verilog
Hello there, I'm running into the problem that I don't know how to do this. I want to write state machine to run 2 conditions on my project. When I turn on machine, I want it runs 1st cond...
Altera_ForumHonored Contributor
Honored Contributoryup, you're right. I'm a bit old-fashioned ;-)
But you must admit, this works too.
