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You can achieve this by creating two processes (I don't know how this is called in verilog, I'm more into VHDL).
The first process sets a pre-initialized signal from "State1" to "State2" if it gets a special signal from the second process.
In the second process you put an if-statement like:
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I really dont know what you're on about (your post does not make a lot of sense). A lot of old text books teams the two process method, but the apparent prefered method now is a single process.
to the OP: there are plenty of examples out there - did you try google yet?
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