Looking for state machine in verilog

You can achieve this by creating two processes (I don't know how this is called in verilog, I'm more into VHDL).

The first process sets a pre-initialized signal from "State1" to "State2" if it gets a special signal from the second process.

In the second process you put an if-statement like:

State-Signal = State1
Switch-Signal = 0
Process1:
if (Switch-Signal = 1)
{
    Set State-Signal to "State2"
}
Process2:
if (State-Signal = State1) then
{
    Your code for State1
    if (time is up)
    {
        Switch-Signal = 1
    }
}
else
{
    Your code for State2
}

this is a very raw example, how it is done normally. You can also use a switch-case-statement instead.

You can also check if the time is up in process1 and then set state2 there.