Looking for FPGA that can have FF and shift register that can clock at 1GHz

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What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled?

You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.

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Wow, I don't know FPGA can receive analog signal now!!!

The analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.

You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?

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No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...

But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?

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If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.

If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.

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contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.

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You can have ADC in FPGA now?

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The FPGA on this board is the Stratix II. Altera has Stratix V devices now.

The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.

You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.

Cheers,

Dave

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Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?

I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?

Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.

Alan

--- Quote Start ---

What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled?

You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.

--- Quote End ---

Wow, I don't know FPGA can receive analog signal now!!!

The analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.

You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?

--- Quote Start ---

No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...

But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?

--- Quote End ---

If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.

If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.

--- Quote Start ---

contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.

--- Quote End ---

You can have ADC in FPGA now?

--- Quote Start ---

The FPGA on this board is the Stratix II. Altera has Stratix V devices now.

The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.

You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.

Cheers,

Dave

--- Quote End ---

Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?

I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?

Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.

Alan

Hi Alan:

Dave gave some good advice. Usually when dealing with data at that rate, it's coming into the FPGA through the Serdies or LVDS inputs:

Altera has serdies in their Cyclone, Arria, and Stratix Families, (Look for GX/GT in the part number)

Basically Cyclone is low end, Arria is mid range and Stratix is the high end parts. (Fasted, biggest, most power)

Pete

Hi

I posted a long thread this morning and it never show up. I even posted it again and nothing happen. It just said it will be waiting for moderator to moderate. Here is the original post:

quote=dwh@ovro.caltech.edu

What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled?

You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.

Wow, I don't know FPGA can receive analog signal now!!!

The analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.

You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?

--- Quote Start ---

No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...

But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?

--- Quote End ---

If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.

If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.

quote=dwh@ovro.caltech.edu

contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.

You can have ADC in FPGA now?

quote=dwh@ovro.caltech.edu

The FPGA on this board is the Stratix II. Altera has Stratix V devices now.

The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.

You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.

Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?

I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?

Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.

Alan

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I posted a long thread this morning and it never show up. I even posted it again and nothing happen. It just said it will be waiting for moderator to moderate.

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You can send it to me directly (my forum name is my email address) and I'll post it.

Cheers,

Dave

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You can send it to me directly (my forum name is my email address) and I'll post it.

Cheers,

Dave

--- Quote End ---

Do you mean email to dwh@ovro.caltech.edu?

Post received from Alan via email:

--- Quote Start ---

What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled?

You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.

--- Quote End ---

Wow, I don't know FPGA can receive analog signal now!!!

In my project,the analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.

You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?

--- Quote Start ---

No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...

But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?

--- Quote End ---

If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.

If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.

--- Quote Start ---

contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.

--- Quote End ---

You can have ADC in FPGA now?

--- Quote Start ---

The FPGA on this board is the Stratix II. Altera has Stratix V devices now.

The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.

You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.

Cheers,

Dave

--- Quote End ---

Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?

I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?

Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.

Alan

Hi Alan,

You have misunderstood. I was warning you that an FPGA expects a digital signal. Re-read my post. The digital signal requirements for LVDS and SERDES are that the signal amplitude be 350mVpp to 400mVpp. If your signals do not have many toggles, then they would also need to be DC coupled to the digital inputs, with an appropriate bias voltage applied.

Your signal *does not* meet these requirements, so you need to decide how you are going to interface your signal to the FPGA.

The board I provided a link to has a dual 1GHz ADC interfaced to an FPGA. The ADC is *not* part of the FPGA.

If you only care about the time at which your pulses occur, and not their amplitude, then you might be able to use a limiting amplifier with high gain, and then interface that to the FPGA inputs.

Cheers,

Dave

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I am not familiar with SERDES

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SERDES = serializer/deserializer. Its a fancy name for a high-speed parallel-to-serial shift-register in the transmit path, and a high-speed serial-to-parallel shift-register in the receive path. FPGAs have hardened silicon blocks in their I/O cells that can operate at up to 28Gbsps in the highest (most expensive) devices. The lower-end devices have 3.5Gbps SERDES.

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what is In-Phi?

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Its a company. Google it.

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Does SERDES have logic block that I can implement the coincident detector and adder?

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No, not for your application. The SERDES blocks have pattern detectors that can be used for digital link byte/word-alignment.

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Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.

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Take the time to read, and re-read the advice people give you, then ask more questions.

Cheers,

Dave