Looking for a Simulator that supports SV Assertions

Hello, I wanted to give some more information. In the hardware development branchI work in we have been using the simulator built-in the Quartus tool. We usually run a simulation that does a few reads and writes and then call the design good, therefor our sims are usually short.

Some in the branch are switching to ModelSim that comes with the Quartus subscription. I'm learning about testbenches and from what I have read you can set up the test bench to run thousands of read/write transactions and have the test bench verify each transactions. This appeals to me because I won't have to scroll through waveforms trying to decipher if these are working.

I've been reading about the SystemVerilog Verfication model and was wondering if I only want to automate my testing will SystemVerilog assertions be sufficient? This would reduce the cost of the simulator. To implement everything described in SV for Verification drives up the cost of a simulator.

Thanks,

joe