Lock a clock to a 8B10B data stream?

You are correct. The recovered CDR clock cannot be used as the reference clock for a TX PLL. The reason for this is jitter performance. What you can do is provide an external clock of the same frequency. You can then use a phase-frequency detector to adjust your external clock to match the CDR clock. One example of this is found in Altera's SDI video reference design which you can find under the IP of your Quartus installation. I believe 9.0 and 9.1 even have a version for Arria II GX.