--- Quote Start ---
Yes, I totally get the whole overview 2 posts above.
--- Quote End ---
Ok.
--- Quote Start ---
But I have no plan to use SOPC or Avalon, partly because I don't want to be tied to them, and partly because there are implementations out there I can model on that don't pre-req any or all of that.
--- Quote End ---
The recommendation is more from the standpoint of being able to leverage the existing, working infrastructure. Then you can incrementally remove the Avalon logic.
--- Quote Start ---
If I had been designing a new system from scratch, for a real commercial purpose, then perhaps I'd be more inclined to use these tools, which seem to be step up a level in productivity.
--- Quote End ---
Its not so much the tool we're interested in here, its the logic. The Flash interface, the SRAM interface, and the DDR controller. Altera/Terasic will supply those controllers with an Avalon interface. So to use them, its easier to bite the bullet and use them they way they were intended.
Here's another way to look at this; create an SOPC system containing a Flash, SRAM, and DDR controller, and an Avalon-MM master interface. Your Z80 external bus then just needs to map onto that Avalon-MM master interface. That Z80-to-Avalon-MM bridge can be part of the SOPC system, or can be external to it.
The SOPC system is just a means-to-an-ends.
--- Quote Start ---
My problem is as was originally stated, how to pre-load various forms of memory on the DE1 card, as simply as possible, given my current tooling.
--- Quote End ---
There's probably a Flash programmer for the board. That'll be based on something like an SOPC System containing a JTAG-to-Avalon-MM slave, or a PFL slave, and that design would be loaded into the FPGA, and then used to access and program the Flash. You could use that blindly to program the flash contents.
--- Quote Start ---
Once, its in there, given the pre-existing success of others, I think my design should work fine.
--- Quote End ---
That is true, assuming you have some logic to access the flash and copy it to SRAM or SDRAM.
--- Quote Start ---
The SDRAM controller thought I had was this:
The mechanism to load SDRAM might involve a special .pof downloaded to the FPGA (isn't that how Control Panel works?), and this could include refresh logic.
But then I'd need to download my real .pof, also with refresh, and I'm wondering how long the SDRAM lasts before losing content, in the period in which the new .pof is being programmed into the FPGA.
--- Quote End ---
It would not survive the reprogramming of the .pof.
You can load the SDRAM from your PC, however, you need to know how to use the JTAG interface. You can use a JTAG-to-Avalon-MM master inside an SOPC system, or you can just use the master directly, and interface to its Avalon-MM master interface (I'm sure its no more complicated than a Z80 external bus). Or you can use the SLD Virtual JTAG component directly.
The complicated part is that your JTAG interface and Z80 will both want to access the SDRAM, and so you need an arbiter. Its not hard to design, but its the kind of thing you get in SOPC Builder 'for free' so to speak.
So, you could build an SOPC system with the 'standard' memory interfaces provided by the DE1 examples, add a JTAG-to-Avalon-MM master to that, and use it to write to the memory on the board. Once you've convinced yourself that all works, you could add another Avalon-MM master interface and map your Z80 onto that. Then you can decide whether you want to replace the DE1 memory controllers with your own designs.
Cheers,
Dave
Honored Contributor
