Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
My QSYS component uses single IP which is counter IP and I haven't any problem with it. My design hasn't any others IP. I made it robust for any kind of FPGA from any companies. Why do I obtain problem with licences for my own design in Quartus 17.1 lite edition? Best Regards,Tgel111