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Altera_Forum
Honored Contributor
9 years agoHi guys i really need help here,
i know it's supposed to be simple but i guess im missing something... this is what i want to acheive: LED1 <= "1"; # Done # 1 seconds delay # Done - frequency divider generated 50Mhz to 1Hz LED2 <-"1"; thats it, as simple as that. and i cant seems to make it happen. all i get is a blinking led in 1 seconds delay : would appriciate any assistance here !
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity test_mode_tst is
port (
CLK_50MHz: in std_logic;
IF1: IN STD_LOGIC; --InfraRed 1
IF2: IN STD_LOGIC; --InfraRed 2
LED1:buffer STD_LOGIC; --LED1
GRID1:buffer STD_LOGIC; --GRID1
GRID2:buffer STD_LOGIC --GRID1
);
end test_mode_tst;
architecture Behavioral of test_mode_tst is
signal Counter: std_logic_vector(24 downto 0);
signal CLK_1Hz: std_logic;
begin
LED1 <= IF1 and IF2;
Prescaler: process(CLK_50MHz)
begin
if rising_edge(CLK_50MHz) then --everytime clk50 is on a rise
if Counter < "1011111010111100001000000" then --if counter smaller than 25,000,000
Counter <= Counter + 1;
else
CLK_1Hz <= not CLK_1Hz;
Counter <= (others => '0');
end if;
end if;
end process Prescaler;
one_shot: process (Counter,GRID1,GRID2)
BEGIN
if (Counter = 0) then
if (LED1 = '1') then --add and next compilation!!!! if led1='1' AND counter =0 then act
GRID1 <= CLK_1Hz;
else
GRID1 <= '0';
end if;
if (GRID1 = '1') and (LED1 = '1') then
GRID2 <= GRID1;
else
GRID2 <= '0';
end if;
end if;
end process one_shot;
end Behavioral;