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Altera_Forum
Honored Contributor
9 years agoi cant seems to get it working for 5 sec' thought...
can you help me see what i'm missing?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity mode_one IS --Simulating mode_one:free mode
--generic (width1s : integer := 1); --Pulse width of 1 seconds
port( clk_in: IN STD_LOGIC; --50Mhz DE2 input.
IF1: IN STD_LOGIC; --InfraRed 1
IF2: IN STD_LOGIC; --InfraRed 2
LED1:buffer STD_LOGIC; --LED1
GRID1:buffer STD_LOGIC; --GRID1
GRID2:buffer STD_LOGIC); --GRID1
END mode_one;
architecture behave OF mode_one IS
signal counter: integer range 50000000 downto 0; --1st process -divider- internal memories
signal clk_out: std_logic; --1st process -divider- internal memories
--signal cnt: integer range 0 to width1s; --2nd process -oneshot- internal memories
BEGIN
LED1 <= IF1 AND IF2;
divider: process(clk_in) --process frequency divider
BEGIN
IF clk_in'EVENT AND clk_in = '1' THEN --Calculating untill counter =25M
if counter = 50000000 then --If counter reached 50mhz
counter <=0; --Reset counter
ELSE counter <= counter+1;
end if;
end if;
end process;
oneshot: process (clk_out) --Process actions with delay
BEGIN
if counter <= 0 then --If X has been counted perform the following
GRID1 <= LED1;
GRID2 <= LED1;
end if;
end process oneshot;
end behave;