'Leaving target processor paused'

When i found this problems with my own designs would be, all the time, that i have surpased the fmax acceptable for the system/FPGA i was running on

Maybe with a time constraining you will fix this.

What i have found to work is (obviously) to low the clock speed to slower values.

(For example, NIOS II running over 110 MHz in a 7 speed grade Cyclone II would fail to verify; after making the clock 100MHz, it would run find)