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Honored Contributor
Honored ContributorLE carry chain
I'm trying to implement LE carry chain using low level primitives. L_0:LCELL
PORT MAP (
in0,out0
);
D_0:DFFEAS
PORT MAP(
d=>out0,
q=>delay(0),
c...
Altera_ForumHonored Contributor
Honored ContributorHi FvM,
I am struggling with a tapped delay line using the carry chain of the FPGA. My intention is to create a delay of 100-150 ps - kind of TDC on FPGA. But I have several problems concering implementation on my Cyclone I. (see last thread on this page.) thank you. bye
