LE carry chain

Hello,

I am trying to implement a programmable delay using the carry chains. (TDC on FPGA!)

I tried to realize the approach presented in most of the papers. (N Fulladders connected to each other Cout from the previous Adder is the Cin of the subsequent one ) .

The simulation (modelsim) delivers acceptable results but on the hardware it didnt worked properly. I guess that i have to use the dedicated carry chain on the FPGA (cyclone I). Furthermore, I have to keep an eye on Constraints and Timing, but i have never worked with this before.

So, I hope that someone of you have any experience with this topic.

I apprecaite for help.

Regards

Solino