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Altera_Forum
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17 years ago

LE carry chain

I'm trying to implement LE carry chain using low level primitives. L_0:LCELL PORT MAP ( in0,out0 ); D_0:DFFEAS PORT MAP( d=>out0, q=>delay(0), c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hello,

I am trying to implement a programmable delay using the carry chains. (TDC on FPGA!)

I tried to realize the approach presented in most of the papers. (N Fulladders connected to each other Cout from the previous Adder is the Cin of the subsequent one ) .

The simulation (modelsim) delivers acceptable results but on the hardware it didnt worked properly. I guess that i have to use the dedicated carry chain on the FPGA (cyclone I). Furthermore, I have to keep an eye on Constraints and Timing, but i have never worked with this before.

So, I hope that someone of you have any experience with this topic.

I apprecaite for help.

Regards

Solino