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Honored Contributor
Honored ContributorLE carry chain
I'm trying to implement LE carry chain using low level primitives. L_0:LCELL
PORT MAP (
in0,out0
);
D_0:DFFEAS
PORT MAP(
d=>out0,
q=>delay(0),
c...
Altera_ForumHonored Contributor
Honored ContributorI've been yet implementing delay chains in logic cells by applying keep attribute to wire signals, as described e.g. in the stratix cookbook (Advanced Synthesis Cookbook). It's straightforward and works with all FPGA families without considering internal details.
I see, that a TDC design (combination of delay chain and DFFs) could utilize carry chains to achieve a compact structure and (hopefully) small delays. It's most likely possible by device specific WYSWYG LCELL primitives. The cookbook has some Stratix examples with direct definition of carry chains. But I never used this. I was basically able to place and connect cycloneiii_lcell_comb elements in a design, that have been kept during synthesis. But I don't yet know the binary LUT_MASK coding necessary for a meaningful logic function.
