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Honored Contributor
Honored ContributorLE carry chain
I'm trying to implement LE carry chain using low level primitives. L_0:LCELL
PORT MAP (
in0,out0
);
D_0:DFFEAS
PORT MAP(
d=>out0,
q=>delay(0),
c...
Altera_ForumHonored Contributor
Honored Contributor1. The RTL apparently belongs to a different VHDL source, cause the instance name of the CARRY_SUM instance is different.
2. Apart from this, it's completely matching the code to my opinion. I don't see, what should be missing. 3. I don't understand, how carry sum is related to logic cell delay line and what you want to achieve with the shown code.
