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plancheres's avatar
plancheres
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Large uTh in timing analysis

Hello, I'm working with Arria 10 and I'm trying to optimize timing in a design which appears to be congested due to excessive routing delays added by the compiler to meet hold timing. (The congestio...
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  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Based on engineering input, the hold times will vary depending on how the LAB is configured. Factors such as HS/LP (High Speed/Low Power), the amount of borrowing, and the settings for the Flip-Flop and LUT will all influence the reported uTh.


    As you may already know, different timing models may also affect the uTh.


    Without a design or project, it is difficult to determine what might be contributing to the high uTh at the moment.

    Btw, I’m glad to know the timing issue is solved.


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Thank you for acknowledging the solution provided.

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com', view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan