Forum Discussion

plancheres's avatar
plancheres
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Large uTh in timing analysis

Hello, I'm working with Arria 10 and I'm trying to optimize timing in a design which appears to be congested due to excessive routing delays added by the compiler to meet hold timing. (The congestio...
Fpga Devkit
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Based on engineering input, the hold times will vary depending on how the LAB is configured. Factors such as HS/LP (High Speed/Low Power), the amount of borrowing, and the settings for the Flip-Flop and LUT will all influence the reported uTh.


    As you may already know, different timing models may also affect the uTh.


    Without a design or project, it is difficult to determine what might be contributing to the high uTh at the moment.

    Btw, I’m glad to know the timing issue is solved.


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Based on engineering input, the hold times will vary depending on how the LAB is configured. Factors such as HS/LP (High Speed/Low Power), the amount of borrowing, and the settings for the Flip-Flop and LUT will all influence the reported uTh.


As you may already know, different timing models may also affect the uTh.


Without a design or project, it is difficult to determine what might be contributing to the high uTh at the moment.

Btw, I’m glad to know the timing issue is solved.


Regards,

Richard Tan


  • plancheres's avatar
    plancheres
    Icon for New Contributor rankNew Contributor
    2 years ago

    So the congestion may have led to some LABs being borrowed that weren't optimally configured, leading to larger uTh.

    Thanks Richard.