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FPGAs have no gates, so gate count is not available. What you can get is a count of LUTs, registers, ram, multipliers etc used in the design (ie. the basic parts in the FPGA). This is estimated in the synth report and given in the fitter report. In the fit report it also gives these numbers as a %age of the current device.
Power estimation can be done with the PowerPlay power estimator tool :
https://www.altera.com/support/support-resources/operation-and-testing/power/pow-powerplay.html Block diagrams can be found in tools -> netlist viewers ->
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Thanks a lot. I need to compile a design which contains 64 input and 64 output lines. Is there any way to assign pins for those in DE1 board?
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