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GBovi's avatar
GBovi
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5 years ago

JTAG To Avalon Master Bridge sld node index or name set

When I instantiate the JTAGToAvalonMasterBridge, I need to choose the jtag index of this master. Because if I add another bridge I don't want the index of the existing ones changes. Another solution ...
GBovi's avatar
GBovi
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5 years ago

Thank for your reply Eric. This is not my problem.

I can explain it with your example.

I call master_0, master_1 and so on, different variables associated with different masters of my project.

Let's say master_0=JTAG2Avln and master_1=Nios

If now i want to add another master (for example another NIOS) to my project, the order can be redefined and I cannot use the same tcl source

Quartus has an automated system of index association to JTAG nodes.

But I have solved using Design functions. Loading a Design I have always the same symbolic name linked to the JTAG master, whatever index calculated.

It's a solution, even if not so flexible, and I'm still trying to solve on the FPGA side, locking JTAG SLD Index of each master.

Thank you Eric