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Altera_Forum
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8 years ago

JTAG timing constraints

Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hello Anand,

Yes it's a Max 10, (10M08, UBGA-169, Single Supply. 10M08SAU169C8G)

Pl see the attached PNG file.

- Basically I have pull-ups on the TDI and TMS lines (10K to 2.5V), and pull-down on the TCK line (1K to GND).

- TDO is direct to the FPGA.

- On pin 4 of the JTAG header, 2.5V is supplied. (These first 3 points I did, as per the Guidelines document).

- JTAG pins on the FPGA are on Bank 1B, which is at 3.3V, as this is a single supply chip.

- The 3 configuration related resistors (nConfig, nStatus and ConfigDone) are on Bank 8 of the chip, which I am using at 2.5V and these pins have 10K resistors, pulled up to 2.5V.

I have used same connections on my Prototype board and I am able to do JTAG configuration without any problems.

On my newer version of the board nStatus is always staying low, though JTAG is able to read the Device ID.

I have nearly spent two full days without making any further headway, despite searching a lot online for relevant info, so any tips / debug strategy would be appreciated.

Thanks,