JTAG timing constraints

@Leonardo:

The latest cookbook example for JTAG is lot more extensive than your example. It also includes fitter-specific constraints, implying these *do* have effect?

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if { $use_fitter_specific_constraint && [string equal quartus_fit

$::TimeQuestInfo(nameofexecutable)] } {

# Define a different set of timing spec to influence place-and-route

# result in the jtag clock domain. The slacks outside of FPGA are

# maximized.

}

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Our JTAG hardware routing is nothing special, and we always use USB Blaster I which only supports 6 MHz. Considering each clock cycle is a whopping 166 ns, I find it hard to believe that JTAG constraints could pose an issue at all, but they do. I conclude then that the constraints (sometimes adversely) affect the FPGA logic.