Honored ContributorI just found out that the documentation for the Virtual Jtag megafunction was updated. A very nice surprise was to find that now, the Jtag SLD Hub infrastructure is fully officially documented.
Seems that somebody at Altera is listening :) Still no documentation about the USB Blaster interface, or about Jtag access APIs from the host side. But this is certainly a step in the right direction.
Honored ContributorOut of curiosity, what are you doing with this? Writing your own controller? (I did something with this when it first came out, and for my needs, the documentation was enough, but I've always felt a lot was capable with this that wasn't being taken advantage of...)
Honored ContributorI'm not using my own controller, at least not a hardware controller as when using a micro to control the Jtag interface. I am accessing virtual jtag nodes from a PC at the application level.
Before this update, the only documented way to access the SLD hub was using TCL scripts. TCL scripts are good enough in many cases, in others you need your own application. In my specific case, if Altera would provide a documented API at the C level, then I wouldn't really need the SLD hub low level info. Short of that API, I used the SLD hub infrastructure, accessing the FTDI USB Blaster driver directly.Honored ContributorReally nice. It seems to be neccessary to browse MF user guides for updates from time to time. I also see a late echo to previous user requests. Thanks!
To my opinion, a documentation of sld_hapi.dll interface would perfectly supplement V2.0 ug_virtualjtag. @Rysc: There are many possible applications, I think. As an example, I'm just now finishing a design, that uses a Source&Probe instance included with the final FPGA image as test interface, operated through a PC user application. You either need an interface to the Quartus JTAG protol stack or have to understand the virtual JTAG protocol at the wire level to access VJTAG instances in the design. I regard the rich VJTAG infrastructure provided by Quartus and Altera FPGA as an important product feature. With some support, it could be further opened to user applications.
