Altera_ForumHonored Contributor14 years agoJtag signal integrity program Hi all: I have develop a custom board of stratix iv gx, with jtag and AS configuration. I find: 1) One week before, I can debug the fpga through jtag with USB-blaster cable(Rev C), and con...Show More
Altera_ForumHonored Contributor14 years agoI change some capacity value from 0.01uf or more less to 0.1uf.
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