To resume,
On cyclone II, (
http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1_06.pdf figure 13-25)
JTAG pin 1 connected to FPGA TCK with 1k pulled down.....JTAG pin 2 connected to GND
JTAG pin 3 connected to FPGA TDO..................................
jtag pin 4 directly connected to vccio. JTAG pin 5 connected to FPGA TMS with 1k Pulled UP.........
jtag pin 6 no connect (for usb blaster and byteblaster ii). JTAG pin 7 No Connect....................................................JTAG pin 8 No Connect.
JTAG pin 9 to FPGA TDI with 1k Pulled UP.........................JTAG pin 10 to GND.
Is it right ?
250$ burnt for just one pin :eek: :d