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I would like to interface Cyclone IV JTAG interface via both ways :
1. JTAG USB blaster.
2. FTDI FT2232 MPSSE interface.
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Do you understand how to implement this?
The USB-Blaster uses a parallel interface for communication between the FT245 and a MAX CPLD. The MAX CPLD interprets bytes over the cable, and then manipulates the JTAG pins on another FPGA. Are you planning on making your Cyclone IV FPGA act as a USB-Blaster?
The MPSSE mode can just be tied to the JTAG pins on the Cyclone IV. The Arrow BeMicro board essentially follows this scheme.
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I am using VCCIO 3.3V in Jtag bank and in figure 8-23 in cyclone IV handbook its says to connect JTAG voltages TDIpullup,TMSpullup and PIN4 JTAG connector to VCCA = 2.5v.
It says that---
""All I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 . You must power up the VCC of the download cable with a 2.5-V supply from VCCA"
My problem is when interfacing Cyclone via FT2232.
ft2232 has 3.3v I/Os.
Will it be safe???
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The figure shows a direct connection from the programmer to the FPGA pins, so the description is being conservative (note the comment regarding third party programmers).
Personally, I would buffer the TMS/TCK/TDI signals from the header using TinyLogic buffers, and buffer the TDO output to the cable with another TinyLogic buffer. The header power pin can then 3.3V, and the TinyLogic TMS/TCK/TDI buffers can be driven from your VCCIO voltage, and the TDO buffer driven by 3.3V. If your VCCIO bank voltage is lower than 2.5V, then use a dual-power rail buffer (TI and Fairchild both have devices).
In this scheme, you are isolating your expensive and hard-to-rework FPGA from your USB-Blaster cable or cheap knock-off cable. If something goes wrong, and you blow a TinyLogic buffer, they are easy to replace.
Cheers,
Dave
Honored Contributor
