JTAG connection issue

Yes, this sounds exactly like a signal integrity issue. The newer Altera USB-Blaster has a flexi-rigid cable to the target instead of standard ribbon cable, like the Terasic Blaster. That is to combat exactly this issue.

I'd remove the 100R resistors - short them out. You might consider keeping a smaller value on TCK. The TDO should certainly improve without a series termination - the TDO buffer out of the FPGA is not very strong.

The voltage levels you refer to being a little low could easily be your oscilloscope and probing (perhaps) not being up to the job. However, I wouldn't worry about that for the minute.

Do you have particularly long JTGA traces on your board?

Try changing the resistors and see if that improves things.

Cheers,

Alex