Forum Discussion
Altera_Forum
Honored Contributor
16 years agoUnfortunately, your post doesn't bring an approach to explain the issue, everything seems right so far.
MSEL = "000" is suggested in the device handbook for JTAG only configuration, but I didn't ever use it. Seeing correct logic levels from all JTAG signals should ususally be sufficient to validate the ByteBlaster operation. Finally there is a risk, that the FPGA has been damaged during assembly or my massive overvoltages. Personally, I would rather expect some kind of non-obvious wiring error or missing supply connection. I fear, there's no chance to further assist you from a distance.