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Altera_Forum
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16 years ago

JTAG configuration error in CycloneIII

Hi The last week I wrote a post about a problem with the configuration of the EP3C5E144C8N cycloneIII FPGA: ------------- I´m trying to program a EP3C5E144C8N FPGA in JTAG mode using a ByteBla...
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Altera_Forum
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16 years ago

Hi MSchmitt and Frank

Thank you for your answers.

In this application I will use only JTAG, that´s why I connected MSEL 0,1,2 to ground. Is not correct?

I checked with an oscilloscope the JTAG signals arriving to the corresponding pins and they are OK (TDI, TMS and TCK). TCK is normally in 0V and when I press the start button appear a pulse burst with 2.5V of amplitud. The same with TDI and TMS but they are normally in high level and the pulse bursts are inverted. The output signal TDO is normally around 1V but it doesn´t change, is that normal?

If the ByteblasterII is sending TDI, TMS and TCK signals, could it be damaged?

L1-L3 are ferrite beads 0603 case.

U4 is a High Speed LDO Regulator (XC6214 Series).

I used a 10MHz external clock in my circuit (clk3), but I have not connected it yet, I will use it once programmed the FPGA as timing sequence.

Thanks for the advice in use a 100nF near each supply pin, I will put in the board.

I Hope you can help me, thanks again