Honored Contributor
Honored ContributorIf 4.7u || 100 pF on each power node is all your bypassing, you may experience problems in device operation. I would suggest additional 100n near each supply pin. But the JTAG chain should be accessible.
I also stumbled upon nCONFIG tied to VCC. But Altera says, connect it to logic high with JTAG only configuration, the same with DCLK/DATA0 connected to ground. So I don't see an obvious error in the schematic. Personally I think, providing an optional AS flash would be a good idea. There's always a possibility, that ByteBlaster is defective. If you can't verify it's operation with a different board, you should check, that all JTAG signals are arriving at the FPGA pins with correct level. According to the Cyclone III device handbook, irregular power supply sequencing can be an issue, e.g. no valid VCCIO present when VCCINT and VCCA, that control the POR circuit, have reached nominal levels. But I don't think that this is likely to cause problems in your case.
