Hi everyone,
Sorry for the delay in my answers, I was quite busy trying to understand how the JTAG chain debugger works.
This message is an answer to
dwh@ovro.caltech.edu and its 30th May post concerning the low level JTAG interface and the Avalon-to-xxx bridge.
I will provide more details about my testing philosophy because your solutions are not adapted to it:
- It's prefered to only implement the logic to be tested inside the FPGA in order to be as close as possible as the final ASIC configuration.
- I'm using QUartus and a Cyclone II FPGA at the moment, but it could change in the future, I don't want my testbench to be dependant of Altera's tools as the Avalon bus.
The final goal of those FPGA tests is to validate VHDL codes for ASIC tape-out. The final ASIC device has to have high level of maturity.
I'm planning to develop different behavioural models of the ASIC top-level and submodules, which will produce the same outputs as the DUT. Results will then be compared to actual DUT inputs/outputs to detect bugs.
I want to quickly and easily get the DUT I/O signals, that's why I want to use JTAG chain.
At the moment, I'm using the JTAG chain debugger, but I'm searching to use it with scripts, because the GUI is not efficient for long test scenario and because it is a repetitive task, it could then be automated.
- If you could give me information about how to use the JTAG chain debugger with scripts, I would appreciate.
- If it's not possible, is there any other way to manage the JTAG chain via the USB Blaster cable on a DE1 development board?
I'm also always searching for explanation about how the JTAG manages the DUT clock, when JTAG is active. Does it disable the clock, how is it done?
I hope those additional information are clear enough.
Have a good day,
J-B
Honored Contributor
