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Thank you for the information, it can be a useful feature.
However I'm not using any Avalon bus as my system validates different modules which will be integrated to an ASIC.
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You've got a couple of options;
1) Build an Avalon bridge to whatever bus protocol your ASIC works from. Ignore the fact that this example uses the Avalon protocol, use it to design a JTAG-to-programmable I/O. The main advantage is that the logic is debugged, working, and supported by Altera.
2) Use the low-level JTAG interface to design your own test logic. See these two documents:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf)
http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf (
http://www.ovro.caltech.edu/%7edwh/correlator/pdf/vjtag.pdf)
The first shows the protocol of the JTAG-to-Avalon-ST component, from which you could construct whatever bridge you like. The second shows the lowest-level JTAG interface.
The zip file contains Modelsim simulations, so you can use those to develop your debug logic and decide what interface you like.
Cheers,
Dave
Honored Contributor
