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So you have built your own SFL rather than using the existing protocol?
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Yes, exactly. There is no documentation (not too much) about protocol used in SFL, so I couldn't be able to write a software for my DSP to use SFL.
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But if I want to write a program (sof, rpd file, I still don't know which is appropriate) into EPCS, do I really need to use Virtual JTAG?
JTAG is necessary for SFL, but not for altASMI_parallel megafunction? am I right?
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I program RBF into EPCS4 Flash.
Virtual JTAG is for communicating with your design in FPGA.
If you want to program EPCS using Altera software just stay with SFL. If you need to program it without using Altera software you need to 'hack' SFL protocol or create your own design (like mine). I don't see other exists.
Honored Contributor
