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Norick's avatar
Norick
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7 years ago
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Jitter performance due to non-dedicated routing?!

Hello I am using: Quartus 18.0 Max10 Now I get following warning message: Warning (15064): PLL "... output port clk[0] feeds output pin "ADC_CLK~output" via non-dedicated routing -- jitter per...
  • a_x_h_75's avatar
    a_x_h_75
    7 years ago

    I'm only assuming the "two issues" are true for your design. Without knowing more of your device/pinout I can't comment.

    Regardless of that, I'd change it to use a single PLL using two clock outputs, ensuring you use the appropriate FPGA pin, associated with the right PLL, for ADC_CLK.

    Cheers,

    Alex

a_x_h_75's avatar
a_x_h_75
Icon for Contributor rankContributor
7 years ago

I'm only assuming the "two issues" are true for your design. Without knowing more of your device/pinout I can't comment.

Regardless of that, I'd change it to use a single PLL using two clock outputs, ensuring you use the appropriate FPGA pin, associated with the right PLL, for ADC_CLK.

Cheers,

Alex