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CTu001's avatar
CTu001
Icon for New Contributor rankNew Contributor
7 years ago

JIC programming process shows successful, but the FPGA Configuration Sequence looks abnormal.

Debug information: device: 5CEFA4M13I7N MSEL[4:0] setting: 10011 related signal observation: nSTATUS is high nCONFIG toggled repeatedly CONF_DONE is low By the way, what is the difference be...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Chien-Hui Tu, nSTATUS is toggling, that means the configuration is not successful. Can you try to change the MSEL to 10010? Also, can you check if AS mode is selected in the Quartus Design? Regards, YL