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I retest the calibrations and they are correct
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You missed explaining what these calibrations are :)
If the calibrations are something you store in the RAM of the FPGA, then the EPCS device needs to include data to load the RAM with at power on. The EPCS devices are SPI Flash. When the FPGA powers on it is an SPI master that reads flash and copies the contents into its configuration SRAM, that configuration data is your custom design. Read-only memory (ROM) is still FPGA SRAM, but it has no read ports as far as your logic is concerned.
So what is it that is being "compared" when you check the calibration data?
Cheers,
Dave
Honored Contributor
