jesd204b pcs data and link data are inconsistent

Hello,

I found that the link data and pcs data are inconsistent. the UG display device clock should be at the same frequency as the link clock, but I didn't notice it before. In my design, F, M, L = 8, 16, 4, and the rate of each lane is 8G, but I set the device clocks of ADC and FPGA at 100M, the core pll shares the device clock with the jesd204b IP, and outputs a 200M link clock and a 100M frame clock. jesd204b IP outputs 128bit link data and 256bit frame data.I am not sure if the device clk frequency or other reasons cause the data inconsistency, is there any solution?

thanks！