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VMich4
New Contributor
New ContributorI've a problem with PCIe in Arria10. Сoreclkout_hip = 0!
We have developed a module with installed FPGA Arria 10. FPGA - 10Ax022E4F29i3. In the project we use IPCore Pcie (HardIP). Refclk (100MHz) is detected inside FPGA (SignalTap "sees"). But on the outp...
BoonT_Intel
Frequent Contributor
Frequent ContributorAndyN, thanks for help.
Other than reset, what is the sampling clock that you used for signaltap (STP)? If the sampling clock is slower or same frequency compare to the coreclkout_hip. Then you might unable to see it toggling in STP.
