Issue with LVDS_CLOCK_TREE placement on Arria 10

Hi RS,

Thanks for the feedback! So I let Quartus perform auto-assign. The LVDS pin assignment where I was getting errors assigning it to F9/G9, wants to auto assign to AW16. I believe that it tried to place it here, since (as a test) I connected the LVDS internal PLL to an external clock that is on AP18 (which is in the same BANK 2A.

So I'm using a FMC daughtercard which, for this particular design, requires me to connect shared LVDS pairs to the 3G and 3F IO Banks.

So my questions are:

1. It appears my error was related to the fact that is could not place the LVDS at that PIN, and I'm assuming it was due to where I was supplying the refclk for the IOPLL. I don't believe I can use a clock in the 3G/3F banks as an externally supplied refclk for those LVDS pairs (I will do some research to see if the board has anything available). In this case, is there a way to create a "global" refclk inside the FPGA that can be used for the LVDS IOPLL?
2. Is there a way for me to create an LVDS 5 channel TX, that has a shared PLL? Or is there a way for all of these 5 channels to receive the same clock from an external PLL?

Feel free to point me to any docs that can clear this up. I had read through a few, but could not find the answer to what I was looking for (or wasn't sure exactly what to search for)

Thanks!