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Altera_Forum
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14 years ago

Issue with conf_done hosing a Cyclone IV

In a nutshell, it appears that something related to the conf_done pin is borking my FPGA post bitload. Background: I'm programming a Cyclone IV via a micro using PS mode. The conf_done pin g...
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Altera_Forum
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14 years ago

Page 8-32 of the handbook states:

Two DCLK falling edges are required after CONF_DONE goes high to begin the

initialization of the device.

So you should enable and use the INIT_DONE signal, or build in a 2 clock delay from CONF_DONE before you tristate the DCLK and Data 0 pins.

Pete