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If one assume this only relate to flops that always reset to some value as I discussed in original post, this is not a problem. But the real flop in ASIC or may not behave this way. Correct behavior is undefined output from flops (sometimes 0, sometime 1, never known a priori). Therefore, coding this way with left most entry as default state does not address the issue of undefined output from real flop causing the post place and route and hardware behavior to not match RTL functional.
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As many contributors explained, the initialization behaviour with FPGA hardware is compeletey defined. The Quartus synthesis tool also achieves consistency between functional simulation and hardware behaviour, because it codes the initial FSM state with all zero state FFs.
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As for HW, I was testing an FPGA hardware in lab long ago, and it would only work after dozen or so power cycles. Now I think of it, I suspect the guy who did RTL did not reset his state machine written in VHDL.
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I agree with K_J, that the reason is more likely a timing violation by an asynchronously released reset than a missing reset. Clock glitches can have a similar effect. Unfortunately, these effects can't be catched in a functional simulation.
If I understand right, your question can be reduced to "how to achieve a FSM simulation consistent with an ASIC hardware target". I'm convinced, that both VHDL and Verilog HDL have adequate means for this purpose, but probably not in an automatic manner. I assume, that similar to the FPGA target, missing reset is only one of the simple cases, that may cause design failure.
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